/**
  ******************************************************************************
  * @file    stm32f4xx_fsmc.c
  * @author  MCD Application Team
  * @version V1.4.0
  * @date    04-August-2014
 * @brief    This file provides firmware functions to manage the following
  *          functionalities of the FSMC peripheral:
  *           + Interface with SRAM, PSRAM, NOR and OneNAND memories
  *           + Interface with NAND memories
  *           + Interface with 16-bit PC Card compatible memories
  *           + Interrupts and flags management
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_fsmc.h"
#include "stm32f4xx_rcc.h"

/** @addtogroup STM32F4xx_StdPeriph_Driver
  * @{
  */

/** @defgroup FSMC
  * @brief FSMC driver modules
  * @{
  */

/* Private typedef -----------------------------------------------------------*/
const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */
								0x0F, /* FSMC_AddressHoldTime */
								0xFF, /* FSMC_DataSetupTime */
								0x0F, /* FSMC_BusTurnAroundDuration */
								0x0F, /* FSMC_CLKDivision */
								0x0F, /* FSMC_DataLatency */
								FSMC_AccessMode_A /* FSMC_AccessMode */
							       };
/* Private define ------------------------------------------------------------*/

/* --------------------- FSMC registers bit mask ---------------------------- */
/* FSMC BCRx Mask */
#define BCR_MBKEN_SET          ((uint32_t)0x00000001)
#define BCR_MBKEN_RESET        ((uint32_t)0x000FFFFE)
#define BCR_FACCEN_SET         ((uint32_t)0x00000040)

/* FSMC PCRx Mask */
#define PCR_PBKEN_SET          ((uint32_t)0x00000004)
#define PCR_PBKEN_RESET        ((uint32_t)0x000FFFFB)
#define PCR_ECCEN_SET          ((uint32_t)0x00000040)
#define PCR_ECCEN_RESET        ((uint32_t)0x000FFFBF)
#define PCR_MEMORYTYPE_NAND    ((uint32_t)0x00000008)

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup FSMC_Private_Functions
  * @{
  */

/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
 *  @brief   NOR/SRAM Controller functions
 *
@verbatim
 ===============================================================================
                    ##### NOR and SRAM Controller functions #####
 ===============================================================================

 [..] The following sequence should be followed to configure the FSMC to interface
      with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:

   (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);

   (#) FSMC pins configuration
       (++) Connect the involved FSMC pins to AF12 using the following function
            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
       (++) Configure these FSMC pins in alternate function mode by calling the function
            GPIO_Init();

   (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
      the structure member.

   (#) Initialize the NOR/SRAM Controller by calling the function
          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

   (#) Then enable the NOR/SRAM Bank, for example:
          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);

   (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.

@endverbatim
  * @{
  */

/**
  * @brief  De-initializes the FSMC NOR/SRAM Banks registers to their default
  *   reset values.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
  * @retval None
  */
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
{
	/* Check the parameter */
	assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));

	/* FSMC_Bank1_NORSRAM1 */
	if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
	{
		FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
	}
	/* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
	else
	{
		FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
	}
	FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
	FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}

/**
  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
  *         parameters in the FSMC_NORSRAMInitStruct.
  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
  *         that contains the configuration information for the FSMC NOR/SRAM
  *         specified Banks.
  * @retval None
  */
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
{
	/* Check the parameters */
	assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
	assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
	assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
	assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
	assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
	assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
	assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
	assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
	assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
	assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
	assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
	assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
	assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
	assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
	assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
	assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
	assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
	assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
	assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
	assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));

	/* Bank1 NOR/SRAM control register configuration */
	FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
		(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
		FSMC_NORSRAMInitStruct->FSMC_MemoryType |
		FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
		FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
		FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
		FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
		FSMC_NORSRAMInitStruct->FSMC_WrapMode |
		FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
		FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
		FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
		FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
		FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
	if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
	{
		FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
	}
	/* Bank1 NOR/SRAM timing register configuration */
	FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
		(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
		(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
		(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
		(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
		(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
		(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
		FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;


	/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
	if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
	{
		assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
		assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
		assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
		assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
		assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
		assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
		FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
			(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
			(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 ) |
			(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
			(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
			(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
			FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
	}
	else
	{
		FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
	}
}

/**
  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
  *         which will be initialized.
  * @retval None
  */
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
{
	/* Reset NOR/SRAM Init structure parameters values */
	FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
	FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
	FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
	FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
	FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
	FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
	FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
	FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
	FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
	FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
	FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
	FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
	FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
	FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef *)&FSMC_DefaultTimingStruct;
	FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef *)&FSMC_DefaultTimingStruct;
}

/**
  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
	assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
	assert_param(IS_FUNCTIONAL_STATE(NewState));

	if (NewState != DISABLE)
	{
		/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
		FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
	}
	else
	{
		/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
		FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
	}
}
/**
  * @}
  */

/** @defgroup FSMC_Group2 NAND Controller functions
 *  @brief   NAND Controller functions
 *
@verbatim
 ===============================================================================
                    ##### NAND Controller functions #####
 ===============================================================================

 [..]  The following sequence should be followed to configure the FSMC to interface
       with 8-bit or 16-bit NAND memory connected to the NAND Bank:

  (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
      (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
      (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);

  (#) FSMC pins configuration
      (++) Connect the involved FSMC pins to AF12 using the following function
           GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
      (++) Configure these FSMC pins in alternate function mode by calling the function
           GPIO_Init();

  (#) Declare a FSMC_NANDInitTypeDef structure, for example:
      FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;
      and fill the FSMC_NANDInitStructure variable with the allowed values of
      the structure member.

  (#) Initialize the NAND Controller by calling the function
      FSMC_NANDInit(&FSMC_NANDInitStructure);

  (#) Then enable the NAND Bank, for example:
      FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);

  (#) At this stage you can read/write from/to the memory connected to the NAND Bank.

 [..]
  (@) To enable the Error Correction Code (ECC), you have to use the function
      FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
 [..]
  (@) and to get the current ECC value you have to use the function
      ECCval = FSMC_GetECC(FSMC_Bank3_NAND);

@endverbatim
  * @{
  */

/**
  * @brief  De-initializes the FSMC NAND Banks registers to their default reset values.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  * @retval None
  */
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
{
	/* Check the parameter */
	assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		/* Set the FSMC_Bank2 registers to their reset values */
		FSMC_Bank2->PCR2 = 0x00000018;
		FSMC_Bank2->SR2 = 0x00000040;
		FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
		FSMC_Bank2->PATT2 = 0xFCFCFCFC;
	}
	/* FSMC_Bank3_NAND */
	else
	{
		/* Set the FSMC_Bank3 registers to their reset values */
		FSMC_Bank3->PCR3 = 0x00000018;
		FSMC_Bank3->SR3 = 0x00000040;
		FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
		FSMC_Bank3->PATT3 = 0xFCFCFCFC;
	}
}

/**
  * @brief  Initializes the FSMC NAND Banks according to the specified parameters
  *         in the FSMC_NANDInitStruct.
  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
  *         contains the configuration information for the FSMC NAND specified Banks.
  * @retval None
  */
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
{
	uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;

	/* Check the parameters */
	assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
	assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
	assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
	assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
	assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
	assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
	assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
	assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
	assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
	assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
	assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
	assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
	assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
	assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
	assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));

	/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
	tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
		 PCR_MEMORYTYPE_NAND |
		 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
		 FSMC_NANDInitStruct->FSMC_ECC |
		 FSMC_NANDInitStruct->FSMC_ECCPageSize |
		 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 ) |
		 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);

	/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
	tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
		  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
		  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
		  (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);

	/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
	tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
		  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
		  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
		  (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);

	if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
	{
		/* FSMC_Bank2_NAND registers configuration */
		FSMC_Bank2->PCR2 = tmppcr;
		FSMC_Bank2->PMEM2 = tmppmem;
		FSMC_Bank2->PATT2 = tmppatt;
	}
	else
	{
		/* FSMC_Bank3_NAND registers configuration */
		FSMC_Bank3->PCR3 = tmppcr;
		FSMC_Bank3->PMEM3 = tmppmem;
		FSMC_Bank3->PATT3 = tmppatt;
	}
}


/**
  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
  *         will be initialized.
  * @retval None
  */
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
{
	/* Reset NAND Init structure parameters values */
	FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
	FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
	FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
	FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
	FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
	FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
	FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
	FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
	FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}

/**
  * @brief  Enables or disables the specified NAND Memory Bank.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
	assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
	assert_param(IS_FUNCTIONAL_STATE(NewState));

	if (NewState != DISABLE)
	{
		/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{
			FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
		}
		else
		{
			FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
		}
	}
	else
	{
		/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{
			FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
		}
		else
		{
			FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
		}
	}
}
/**
  * @brief  Enables or disables the FSMC NAND ECC feature.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  * @param  NewState: new state of the FSMC NAND ECC feature.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
	assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
	assert_param(IS_FUNCTIONAL_STATE(NewState));

	if (NewState != DISABLE)
	{
		/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{
			FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
		}
		else
		{
			FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
		}
	}
	else
	{
		/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{
			FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
		}
		else
		{
			FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
		}
	}
}

/**
  * @brief  Returns the error correction code register value.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  * @retval The Error Correction Code (ECC) value.
  */
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
{
	uint32_t eccval = 0x00000000;

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		/* Get the ECCR2 register value */
		eccval = FSMC_Bank2->ECCR2;
	}
	else
	{
		/* Get the ECCR3 register value */
		eccval = FSMC_Bank3->ECCR3;
	}
	/* Return the error correction code value */
	return(eccval);
}
/**
  * @}
  */

/** @defgroup FSMC_Group3 PCCARD Controller functions
 *  @brief   PCCARD Controller functions
 *
@verbatim
 ===============================================================================
                    ##### PCCARD Controller functions #####
 ===============================================================================

 [..]  he following sequence should be followed to configure the FSMC to interface
       with 16-bit PC Card compatible memory connected to the PCCARD Bank:

  (#)  Enable the clock for the FSMC and associated GPIOs using the following functions:
       (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
       (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);

  (#) FSMC pins configuration
       (++) Connect the involved FSMC pins to AF12 using the following function
            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
       (++) Configure these FSMC pins in alternate function mode by calling the function
            GPIO_Init();

  (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
      FSMC_PCCARDInitTypeDef  FSMC_PCCARDInitStructure;
      and fill the FSMC_PCCARDInitStructure variable with the allowed values of
      the structure member.

  (#) Initialize the PCCARD Controller by calling the function
      FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);

  (#) Then enable the PCCARD Bank:
      FSMC_PCCARDCmd(ENABLE);

  (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.

@endverbatim
  * @{
  */

/**
  * @brief  De-initializes the FSMC PCCARD Bank registers to their default reset values.
  * @param  None
  * @retval None
  */
void FSMC_PCCARDDeInit(void)
{
	/* Set the FSMC_Bank4 registers to their reset values */
	FSMC_Bank4->PCR4 = 0x00000018;
	FSMC_Bank4->SR4 = 0x00000000;
	FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
	FSMC_Bank4->PATT4 = 0xFCFCFCFC;
	FSMC_Bank4->PIO4 = 0xFCFCFCFC;
}

/**
  * @brief  Initializes the FSMC PCCARD Bank according to the specified parameters
  *         in the FSMC_PCCARDInitStruct.
  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
  *         that contains the configuration information for the FSMC PCCARD Bank.
  * @retval None
  */
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
{
	/* Check the parameters */
	assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
	assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
	assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));

	assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
	assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
	assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
	assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));

	assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
	assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
	assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
	assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
	assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
	assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
	assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
	assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));

	/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
	FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
			   FSMC_MemoryDataWidth_16b |
			   (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
			   (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);

	/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
	FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
			    (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
			    (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
			    (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);

	/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
	FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
			    (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
			    (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
			    (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);

	/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
	FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
			   (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
			   (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
			   (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
}

/**
  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
  *         which will be initialized.
  * @retval None
  */
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
{
	/* Reset PCCARD Init structure parameters values */
	FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
	FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
	FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
	FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
	FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}

/**
  * @brief  Enables or disables the PCCARD Memory Bank.
  * @param  NewState: new state of the PCCARD Memory Bank.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void FSMC_PCCARDCmd(FunctionalState NewState)
{
	assert_param(IS_FUNCTIONAL_STATE(NewState));

	if (NewState != DISABLE)
	{
		/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
		FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
	}
	else
	{
		/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
		FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
	}
}
/**
  * @}
  */

/** @defgroup FSMC_Group4  Interrupts and flags management functions
 *  @brief    Interrupts and flags management functions
 *
@verbatim
 ===============================================================================
             ##### Interrupts and flags management functions #####
 ===============================================================================

@endverbatim
  * @{
  */

/**
  * @brief  Enables or disables the specified FSMC interrupts.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
  *          This parameter can be any combination of the following values:
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
  * @param  NewState: new state of the specified FSMC interrupts.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
{
	assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
	assert_param(IS_FSMC_IT(FSMC_IT));
	assert_param(IS_FUNCTIONAL_STATE(NewState));

	if (NewState != DISABLE)
	{
		/* Enable the selected FSMC_Bank2 interrupts */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{
			FSMC_Bank2->SR2 |= FSMC_IT;
		}
		/* Enable the selected FSMC_Bank3 interrupts */
		else if (FSMC_Bank == FSMC_Bank3_NAND)
		{
			FSMC_Bank3->SR3 |= FSMC_IT;
		}
		/* Enable the selected FSMC_Bank4 interrupts */
		else
		{
			FSMC_Bank4->SR4 |= FSMC_IT;
		}
	}
	else
	{
		/* Disable the selected FSMC_Bank2 interrupts */
		if(FSMC_Bank == FSMC_Bank2_NAND)
		{

			FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
		}
		/* Disable the selected FSMC_Bank3 interrupts */
		else if (FSMC_Bank == FSMC_Bank3_NAND)
		{
			FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
		}
		/* Disable the selected FSMC_Bank4 interrupts */
		else
		{
			FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
		}
	}
}

/**
  * @brief  Checks whether the specified FSMC flag is set or not.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
  * @param  FSMC_FLAG: specifies the flag to check.
  *          This parameter can be one of the following values:
  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
  *            @arg FSMC_FLAG_Level: Level detection Flag.
  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
  *            @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
  * @retval The new state of FSMC_FLAG (SET or RESET).
  */
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
	FlagStatus bitstatus = RESET;
	uint32_t tmpsr = 0x00000000;

	/* Check the parameters */
	assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
	assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		tmpsr = FSMC_Bank2->SR2;
	}
	else if(FSMC_Bank == FSMC_Bank3_NAND)
	{
		tmpsr = FSMC_Bank3->SR3;
	}
	/* FSMC_Bank4_PCCARD*/
	else
	{
		tmpsr = FSMC_Bank4->SR4;
	}

	/* Get the flag status */
	if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
	{
		bitstatus = SET;
	}
	else
	{
		bitstatus = RESET;
	}
	/* Return the flag status */
	return bitstatus;
}

/**
  * @brief  Clears the FSMC's pending flags.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
  * @param  FSMC_FLAG: specifies the flag to clear.
  *          This parameter can be any combination of the following values:
  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
  *            @arg FSMC_FLAG_Level: Level detection Flag.
  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
  * @retval None
  */
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
	/* Check the parameters */
	assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
	assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		FSMC_Bank2->SR2 &= ~FSMC_FLAG;
	}
	else if(FSMC_Bank == FSMC_Bank3_NAND)
	{
		FSMC_Bank3->SR3 &= ~FSMC_FLAG;
	}
	/* FSMC_Bank4_PCCARD*/
	else
	{
		FSMC_Bank4->SR4 &= ~FSMC_FLAG;
	}
}

/**
  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
  *          This parameter can be one of the following values:
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
  * @retval The new state of FSMC_IT (SET or RESET).
  */
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
	ITStatus bitstatus = RESET;
	uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;

	/* Check the parameters */
	assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
	assert_param(IS_FSMC_GET_IT(FSMC_IT));

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		tmpsr = FSMC_Bank2->SR2;
	}
	else if(FSMC_Bank == FSMC_Bank3_NAND)
	{
		tmpsr = FSMC_Bank3->SR3;
	}
	/* FSMC_Bank4_PCCARD*/
	else
	{
		tmpsr = FSMC_Bank4->SR4;
	}

	itstatus = tmpsr & FSMC_IT;

	itenable = tmpsr & (FSMC_IT >> 3);
	if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
	{
		bitstatus = SET;
	}
	else
	{
		bitstatus = RESET;
	}
	return bitstatus;
}

/**
  * @brief  Clears the FSMC's interrupt pending bits.
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
  *          This parameter can be one of the following values:
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
  *          This parameter can be any combination of the following values:
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
  * @retval None
  */
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
	/* Check the parameters */
	assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
	assert_param(IS_FSMC_IT(FSMC_IT));

	if(FSMC_Bank == FSMC_Bank2_NAND)
	{
		FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
	}
	else if(FSMC_Bank == FSMC_Bank3_NAND)
	{
		FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
	}
	/* FSMC_Bank4_PCCARD*/
	else
	{
		FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
	}
}

/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
